SH7065 Datasheet, PDF (935/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Appendix D Restrictions and Caution on HD64F7065S (and HD64F7065A Lots Prior to “1D5”)
2. In case of DSP instructions
(a) PSHA #1,A1
(b) PINC X0,A0
(c) LDC R0,SR
MOVX.W
A1,@R5
Instruction execution is stalled by the
occurrence of register contention.
Saturation operation mode is changed.
As the operation result of DSP instruction is stored directly after the execution of the DSP
instruction, register contention is occurred between (a) PSHA and (b) MOVX instructions, and
the execution of (b) PINC instruction is stalled. The changing of the S bit by (c) instruction is
executed in the CPU before the execution of (b) PINC instruction due to the pipeline control.
As a result, the sequence of (b) and (c) instructions is reversed, and the operation result of the
PINC instruction becomes to be wrong.
In order to avoid the restriction; select one of the followings:
(1) Do not access SR register directly after the Multiply and Accumulate or DSP instructions.
(2) Insert NOP instruction directly before LDC Rn, SR instruction.
(3) Arrange the instruction sequences so that neither multiplier contention nor DSP register
contention can be occurred (no instruction is stalled).
Rev. 5.00 Sep 11, 2006 page 913 of 916
REJ09B0332-0500