SH7065 Datasheet, PDF (14/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

9.2.1 DMA Source Address Registers 0 to 3 (SAR0 to SAR3) .................................... 311
9.2.2 DMA Destination Address Registers 0 to 3 (DAR0 to DAR3)............................ 311
9.2.3 DMA Transfer Count Registers 0 to 3 (DMATCR0 to DMATCR3)................... 312
9.2.4 DMA Channel Control Registers 0 to 3 (CHCR0 to CHCR3) ............................. 313
9.2.5 Next Source Address Registers 0 to 3 (NSAR0 to NSAR3) ................................ 320
9.2.6 Next Destination Address Registers 0 to 3 (NDAR0 to NDAR3)........................ 321
9.2.7 Next Transfer Count Registers 0 to 3 (NDMATCR0 to NDMATCR3)............... 321
9.2.8 Chain Transfer Count Registers 0 to 3 (CHNCNT0 to CHNCNT3).................... 322
9.2.9 DMA Operation Register (DMAOR)................................................................... 322
9.3 Operation........................................................................................................................... 324
9.3.1 DMA Transfer Procedure..................................................................................... 325
9.3.2 DMA Transfer Requests ...................................................................................... 327
9.3.3 Channel Priorities................................................................................................. 330
9.3.4 Types of DMA Transfer....................................................................................... 334
9.3.5 Number of Bus Cycle States and DREQ Pin Sampling Timing ........................... 342
9.3.6 Parallel Operation of DMA and CPU .................................................................. 356
9.3.7 DMA Transfer When External Bus Is Released................................................... 356
9.3.8 Chain Transfer ..................................................................................................... 358
9.4 Example of Use ................................................................................................................. 360
9.4.1 Example of DMA Transfer between On-Chip SCI and External Memory........... 360
9.5 Usage Notes ...................................................................................................................... 360
9.6 DMAC Restrictions........................................................................................................... 362
9.6.1 TEND Output....................................................................................................... 362
9.6.2 Notes on Suspension of Transfer ......................................................................... 362
Section 10 16-Bit Timer Pulse Unit (TPU).................................................................. 365
10.1 Overview........................................................................................................................... 365
10.1.1 Features................................................................................................................ 365
10.1.2 Block Diagram ..................................................................................................... 369
10.1.3 Pin Configuration................................................................................................. 370
10.1.4 Register Configuration ......................................................................................... 372
10.2 Register Descriptions ........................................................................................................ 374
10.2.1 Timer Control Registers (TCR) ........................................................................... 374
10.2.2 Timer Mode Registers (TMDR)........................................................................... 379
10.2.3 Timer I/O Control Registers (TIOR).................................................................... 381
10.2.4 Timer Interrupt Enable Registers (TIER)............................................................. 398
10.2.5 Timer Status Registers (TSR) .............................................................................. 400
10.2.6 Timer Counters (TCNT) ...................................................................................... 403
10.2.7 Timer General Registers (TGR)........................................................................... 404
10.2.8 Timer Start Register (TSTR)................................................................................ 404
10.2.9 Timer Sync Register (TSYR)............................................................................... 405
Rev. 5.00 Sep 11, 2006 page xiv of xxii