SH7065 Datasheet, PDF (255/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 8 Bus State Controller (BSC)
8.2.3 Wait Control Registers (WCR_0 to WCR_3)
The wait control registers (WCR) are 16-bit readable/writable registers that specify the number of
wait state cycles to be inserted in areas 0 to 3.
The WCR registers are initialized to H'FFFE by a power-on reset, but are not initialized in standby
mode.
Bit: 15
14
13
12
11
10
9
8
W3
W2
W1
W0 DSWW3 DSWW2 DSWW1 DSWW0
Initial value:
1
1
1
1
1
1
1
1
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
DSWR3 DSWR2 DSWR1 DSWR0 HWW2 HWW1 HWW0 —
Initial value:
1
1
1
1
1
1
1
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Bits 15 to 12—Wait State Insertion Cycle Specification (W3 to W0): These bits specify the
number of wait states to be inserted in areas 0 to 3.
Bit 15: W3
0
:
1
Bit 14: W2
0
:
1
Bit 13: W1
0
1
:
1
Bit 12: W0
0
1
0
:
0
1
Description
No waits
1 wait
2 waits
:
14 waits
15 waits
(Initial value)
Bits 11 to 8—CS0 to CS3 Space DMA Single Address Mode Write Access Wait State
Insertion Cycle Specification (DSWW3 to DSWW0): These bits specify the number of wait
states to be inserted in writes to spaces CS0 to CS3 in DMA single address mode.
Rev. 5.00 Sep 11, 2006 page 233 of 916
REJ09B0332-0500