SH7065 Datasheet, PDF (573/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 14 Serial Communication Interface (SCI)
14.2.11 FIFO Data Count Register (SCFDR)
The FIFO data count register (SCFDR) is a 16-bit register that indicates the number of data bytes
stored in the transmit FIFO data register (SCFTDR) and receive FIFO data register (SCFRDR).
The upper 8 bits show the number of transmit data bytes in SCFTDR, and the lower 8 bits show
the number of receive data bytes in SCFRDR. SCFDR is initialized to H'00 by a reset, in module
standby mode, and in standby mode. It is also initialized to H'00 by setting the TFRST and RFRST
bits to 1 in SCFCR to reset SCFTDR and SCFRDR to the empty state.
SCFDR can be read by the CPU at all times.
Upper 8 bits:
7
6
5
4
3
2
1
0
—
—
—
T4
T3
T2
T1
T0
Initial value:
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bits 15 to 13—Reserved: These bits are always read as 0 and should only be written with 0.
Bits 12 to 8—Transmit FIFO Data Count (T4 to T0): These bits show the number of
untransmitted data bytes in SCFTDR. A value of H'00 indicates that there is no transmit data, and
a value of H'10 indicates that SCFTDR is full of transmit data. The value is cleared to H'00 by
transmitting all the data, as well as by the above initialization conditions.
Lower 8 bits:
7
6
5
4
3
2
1
0
—
—
—
R4
R3
R2
R1
R0
Initial value:
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bits 7 to 5—Reserved: These bits are always read as 0 and should only be written with 0.
Bits 4 to 0—Receive FIFO Data Count (R4 to R0): These bits show the number of receive data
bytes in SCFRDR. A value of H'00 indicates that there is no receive data, and a value of H'10
indicates that SCFRDR is full of receive data. The value is cleared to H'00 by reading all the
receive data from SCFRDR, as well as by the above initialization conditions.
Rev. 5.00 Sep 11, 2006 page 551 of 916
REJ09B0332-0500