SH7065 Datasheet, PDF (770/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 19 256 kB Flash Memory (F-ZTAT)
19.7 Programming/Erasing Flash Memory
A software method, using the CPU, is employed to program and erase flash memory in the on-
board programming modes. There are four flash memory operating modes: program mode, erase
mode, program-verify mode, and erase-verify mode. Transitions to these modes are made by
setting the PSU, ESU, P, E, PV, and EV bits in FLMCR1.
The flash memory cannot be read while being programmed or erased. Therefore, the program
(user program) that controls flash memory programming/erasing should be located and executed in
on-chip RAM or external memory.
Notes: 1. Operation is not guaranteed if setting or clearing of the SWE, ESU, PSU, EV, PV, E,
and P bits in FLMCR1 is executed by a program in flash memory.
2. When programming or erasing, drive the FWE pin high (programming/erasing will not
be executed if the FWE pin is low).
3. Programming must be executed in the erased state. Do not perform additional
programming on addresses that have already been programmed.
19.7.1 Program Mode
When writing data or programs to flash memory, the program/program-verify flowchart shown in
figure 19.13 should be followed. Performing program operations according to this flowchart will
enable data or programs to be written to flash memory without subjecting the device to voltage
stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a
time.
Following the elapse of 1 µs or more after the SWE bit is set to 1 in flash memory control register
1 (FLMCR1), 128-byte data is written consecutively to the write addresses (the lower 8 bits of the
first address written to must be H'00 or H'80). 128 consecutive byte data transfers are performed.
The program address and program data are latched in the flash memory. A 128-byte data transfer
must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to
the extra addresses.
Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc.
After this, preparation for program mode (program setup) is carried out by setting the PSU bit in
FLMCR1, and after the elapse of 50 µs or more, the operating mode is switched to program mode
by setting the P bit in FLMCR1. The time during which the P bit is set is the flash memory
programming time. See the table in the programming flowchart for the programming time.
Rev. 5.00 Sep 11, 2006 page 748 of 916
REJ09B0332-0500