SH7065 Datasheet, PDF (167/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 4 Clock Pulse Generator (CPG) and Power-Down Modes
4.9.2 Module Stop Control Registers 1 and 2 (MSTPCR1, MSTPCR2)
Module stop control registers 1 and 2 (MSTPCR1, MSTPCR2) are 16-bit readable/writable
registers that specify the module stop mode status.
MSTPCR1 and MSTPCR2 are initialized to H'0000 by a power-on reset, but are not initialized in
software standby mode.
MSTPCR1
Bit: 15
14
13
12
11
10
9
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9
Initial value:
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
8
MSTP8
0
R/W
Bit:
Initial value:
R/W:
7
MSTP7
0
R/W
6
MSTP6
0
R/W
5
MSTP5
0
R/W
4
MSTP4
0
R/W
3
MSTP3
0
R/W
2
MSTP2
0
R/W
1
MSTP1
0
R/W
0
MSTP0
0
R/W
MSTPCR2
Bit: 15
14
13
12
11
10
9
8
MSTP31 MSTP30 MSTP29 MSTP28 MSTP27 MSTP26 MSTP25 MSTP24
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
MSTP23 MSTP22 MSTP21 MSTP20 MSTP19 MSTP18 MSTP17 MSTP16
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 15 to 0—Module Stop 31 to 0 (MSTP31 to MSTP0): These bits specify stoppage of the
clock supply to the corresponding modules. See table 4.16 for the correspondence between the
register bits and modules.
Rev. 5.00 Sep 11, 2006 page 145 of 916
REJ09B0332-0500