SH7065 Datasheet, PDF (556/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 14 Serial Communication Interface (SCI)
Bit 6—Receive FIFO Data Register Full (RDF): Indicates that the received data has been
transferred to the receive FIFO data register (SCFRDR), and the number of receive data bytes in
SCFRDR is equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in
the FIFO control register (SCFCR).
Bit 6: RDF
Description
0
The number of receive data bytes in SCFRDR is less than the receive trigger
set number
(Initial value)
[Clearing conditions]
• In a reset or in standby mode
• When SCFRDR is read until the number of receive data bytes in SCFRDR
falls below the receive trigger set number, and 0 is written to RDF after
reading RDF = 1
• When SCFRDR is read by the on-chip DMAC until the number of receive
data bytes in SCFRDR falls below the receive trigger set number
1
The number of receive data bytes in SCFRDR is equal to or greater than the
receive trigger set number
[Setting condition]
When SCFRDR contains at least the receive trigger set number of receive
data bytes^*
Note: * SCFRDR is a 16-byte FIFO register. When RDF = 1, at least the receive trigger set
number of data bytes can be read. If all the data in SCFRDR is read and another read
is performed, the data value will be undefined. The number of receive data bytes in
SCFRDR is indicated by the lower 8 bits of SCFDR.
Rev. 5.00 Sep 11, 2006 page 534 of 916
REJ09B0332-0500