SH7065 Datasheet, PDF (468/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
Contention between TCNT Write and Clear Operations
If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes
precedence and the TCNT write is not performed.
Figure 10.48 shows the timing in this case.
TCNT write cycle
T1
T2
Pφ
Address
TCNT address
Write signal
Counter clear
signal
TCNT
N
H'0000
Figure 10.48 Contention between TCNT Write and Clear Operations
Rev. 5.00 Sep 11, 2006 page 446 of 916
REJ09B0332-0500