SH7065 Datasheet, PDF (218/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 6 Interrupt Controller (INTC)
6.4.2 Interrupt Response Time
The time from generation of an interrupt request until interrupt exception handling is performed
and fetching of the first instruction of the exception service routine is started (the interrupt
response time) is shown in table 6.8. Figure 6.5 shows an example of pipeline operation when an
IRQ interrupt is accepted.
Table 6.8 Interrupt Response Time
Number of States
Item
NMI, peripheral
Modules
IRQ
Notes
Time for priority
2
3
decision and SR
mask bit comparison
Wait time until end
of sequence being
executed by CPU
X (≥ 0)
X (≥ 0)
The longest sequence
is for interrupt or
address error exception
handling (X = 4 + m1 +
m2 + m3 + m4).
However, the sequence
may be even longer if
an interrupt-masking
instruction follows.
Time from interrupt
5 + m1 + m2 + m3
exception handling
until fetch of first
instruction of exception
service routine is
started
5 + m1 + m2 + m3
SR and PC save and
vector address fetch
are performed.
Response Total
time
Minimum
case
7 + m1 + m2 + m3
10
8 + m1 + m2 + m3
11
At 60-MHz operation:
0.17 to 0.18 µs
Maximum 11 + 2 (m1 + m2 + m3) 12 + 2 (m1 + m2 + m3) At 60-MHz operation:
case
+ m4
+ m4
0.30 to 0.32 µs^*
Legend:
m1 to m4 are the number of states required for the following memory accesses.
m1: SR save (longword write)
m2: PC save (longword write)
m3: Vector address read (longword read)
m4: Fetch of first instruction of interrupt service routine
Note: * When m1 = m2 = m3 = m4 = 1
Rev. 5.00 Sep 11, 2006 page 196 of 916
REJ09B0332-0500