SH7065 Datasheet, PDF (429/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Internal data bus
H
Bus master L
Bus
interface
Section 10 16-Bit Timer Pulse Unit (TPU)
Module
data bus
TCR
Figure 10.3 8-Bit Register Access Operation
(Bus Master ↔ TCR (Upper 8 Bits))
Internal data bus
H
Bus master _L
Bus
interface
Module
data bus
TMDR
Figure 10.4 8-Bit Register Access Operation
(Bus Master ↔ TMDR (Lower 8 Bits))
Internal data bus
H
Bus master L
Bus
interface
Module
data bus
TCR
TMDR
Figure 10.5 8-Bit Register Access Operation
(Bus Master ↔ TCR and TMDR (16 Bits))
Rev. 5.00 Sep 11, 2006 page 407 of 916
REJ09B0332-0500