SH7065 Datasheet, PDF (503/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Pφ
Address
Write signal
Section 11 Motor Management Timer (MMT)
TSR write cycle
T1 T2
TSR address
Status flag
Interrupt
request signal
Figure 11.13 Timing of Status Flag Clearing by CPU
DMAC
read cycle
T1 T2
DMAC
write cycle
T1 T2
Pφ
Address
Source address
Destination
address
Status flag
Interrupt
request signal
Figure 11.14 Timing of Status Flag Clearing by DMA Controller
Rev. 5.00 Sep 11, 2006 page 481 of 916
REJ09B0332-0500