SH7065 Datasheet, PDF (164/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 4 Clock Pulse Generator (CPG) and Power-Down Modes
4.8 Power-Down Modes
4.8.1 States in Power-Down Modes
Table 4.12 shows the conditions for entering the power-down modes from the program execution
state, the state of the CPU and peripheral modules in each mode, and the method of exiting each
mode.
Table 4.12 State of CPU and Peripheral Modules in Power-Down Modes
State
Power-
Down
Mode
Entering
Conditions CPG
CPU
CPU
On-Chip
Registers Memory
On-chip
Peripheral
Modules Pins
Refresh Exiting
Operations Conditions
Sleep
SLEEP
instruction
executed
while SBY
bit is 0 in
SBYCR
Operating Halted
Held
Held
Operating
Operating
Refreshing
1. Interrupt
2. DMA address
error
3. Power-on
reset
Software
standby
SLEEP
instruction
executed
while SBY
bit is 1 in
SBYCR
Halted
Halted
Held
Held
Halted
Halted or Self-
high
refreshing
impedance
1. NMI interrupt
2. Power-on
reset
Hardware Low-level Halted
standby input to
HSTBY pin
Halted
Undefined Held
Halted
High
Refreshing
impedance not
possible
High-level input
to HSTBY pin
during low-level
input to RES pin
Module
standby
function
Setting
MSTP bit
to 1 in
MSTPCR
Operating Operating Held
Held
Specified
modules
halted^*
Held or
initialized
Refreshing
1. Clearing
MSTP bit to 0
2. Power-on
reset
Module
clock
division
Setting
MCLK bit
to 1 in
MCLKCR
Clock to module corresponding to MCLK bit is further divided from master clock
(CKM) or peripheral clock (CKP) set in CPG before being supplied
1. Setting
MCLK bit to
initial value
2. Power-on
reset
Note: * See section 4.9.2, Module Stop Control Registers 1 and 2 (MSTPCR1, MSTPCR2).
Rev. 5.00 Sep 11, 2006 page 142 of 916
REJ09B0332-0500