SH7065 Datasheet, PDF (342/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 9 Direct Memory Access Controller (DMAC)
Bit 0—DMAC Enable (DE): Enables operation of the corresponding channel.
Bit 0: DE
0
1
Description
Operation of corresponding channel is disabled
Operation of corresponding channel is enabled
(Initial value)
When auto-request is specified (with RS5 to RS0), transfer is begun when this bit is set to 1. In the
case of an external request or on-chip module request, transfer is begun when a transfer request is
issued after this bit is set to 1. Transfer can be suspended midway by clearing this bit to 0.
Even if the DE bit has been set, transfer is not enabled when TE is 1, when DME in DMAOR is 0,
or when the NMIF or AE bit in DMAOR is 1.
9.2.5 Next Source Address Registers 0 to 3 (NSAR0 to NSAR3)
Bit: 31 30 29 28 27 26 25 24 23
0
............................
Initial value: — — — — — — — — — ^{. . . . . . . . . . . . . . . . . . . . . . . . . . . .} —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W ^{. . . . . . . . . . . . . . . . . . . . . . . . . . . .} R/W
Next source address registers 0 to 3 (NSAR0 to NSAR3) are 32-bit readable/writable registers that
specify the source address for the next transfer when chain transfer is set. In single address mode,
the NSAR value is ignored when a device with DACK has been specified as the transfer
destination.
Specify a 16-bit boundary address in a 16-bit transfer, and a 32-bit boundary address in a 32-bit
transfer. Operation cannot be guaranteed if a different address is set.
The value of these registers is undefined after a power-on reset, and in hardware standby mode
and software standby mode.
Rev. 5.00 Sep 11, 2006 page 320 of 916
REJ09B0332-0500