SH7065 Datasheet, PDF (560/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 14 Serial Communication Interface (SCI)
Bit 6—Receive LSB/MSB-First Select (RLM): Selects LSB-first or MSB-first mode in data
reception.
Bit 6: RLM
Description
0
LSB-first reception
(Initial value)
1
MSB-first reception
Note: When data is received by 7-bit data length in asynchronous mode, MSB (bit 7) of the
received data is 0 in LSB-first reception mode, and LSB (bit 0) of the received data is 0 in
MSB-first reception mode.
Bits 5 and 4—Clock Bit Rate Ratio (N1, N0): These bits select the ratio of the base clock to the
bit rate.
Bit 5: N1
0
1
Bit 4: N0
0
1
0
1
Description
SCI operates on base clock of 4 times the bit rate
SCI operates on base clock of 8 times the bit rate
SCI operates on base clock of 16 times the bit rate
(Initial value)
Setting prohibited
Bit 3—Break Detect (BRK): Indicates that a receive data break signal has been detected.
Bit 3: BRK
Description
0
A break signal has not been received
(Initial value)
[Clearing conditions]
• In a reset or in standby mode
• When 0 is written to BRK after reading BRK = 1
1
A break signal has been received^*
[Setting condition]
When data with a framing error is received, and a framing error also occurs in
the next receive data (all space “0”)
Note: * When a break is detected, the receive data (H'00) following detection is not transferred
to SCFRDR. When the break ends and the receive signal returns to mark “1”, receive
data transfer is resumed.
Rev. 5.00 Sep 11, 2006 page 538 of 916
REJ09B0332-0500