SH7065 Datasheet, PDF (353/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 9 Direct Memory Access Controller (DMAC)
1. Transfer on channel 0
Initial priority order CH0 > CH1 > CH2 > CH3
Channel 0 is given the lowest
priority.
Priority order after
transfer
CH1 > CH2 > CH3 > CH0
2. Transfer on channel 1
Initial priority order CH0 > CH1 > CH2 > CH3
Priority order after
transfer
CH2 > CH3 > CH0 > CH1
When channel 1 is given the
lowest priority, the priority of
channel 0, which was higher
than channel 1, is also shifted
simultaneously.
3. Transfer on channel 2
Initial priority order CH0 > CH1 > CH2 > CH3
Priority order after
transfer
CH3 > CH0 > CH1 > CH2
Priority after transfer due to issuance
of a transfer request for channel 1 only ^{CH2 > CH3 > CH0 > CH1}
When channel 2 is given the
lowest priority, the priorities of
channels 0 and 1, which were
higher than channel 2, are also
shifted simultaneously. If there
is a transfer request for channel
1 only immediately afterward,
channel 1 is given the lowest
priority and the priorities of
channels 3 and 0 are
simultaneously shifted down.
4. Transfer on channel 3
Initial priority order CH0 > CH1 > CH2 > CH3
No change in priority order
Priority order after
transfer
CH0 > CH1 > CH2 > CH3
Figure 9.3 Round Robin Mode
Rev. 5.00 Sep 11, 2006 page 331 of 916
REJ09B0332-0500