SH7065 Datasheet, PDF (549/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 14 Serial Communication Interface (SCI)
Bit 2—Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor
format is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only
valid in asynchronous mode; it is invalid in synchronous mode and IrDA mode.
For details of the multiprocessor communication function, see section 14.3.3, Multiprocessor
Communication Function.
Bit 2: MP
0
1
Description
Multiprocessor function disabled
Multiprocessor format selected
(Initial value)
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the
built-in baud rate generator. The clock source can be selected from Pφ, Pφ/4, Pφ/16, and Pφ/64,
according to the setting of bits CKS1 and CKS0.
For the relationship between the clock source, the bit rate register setting, and the baud rate, see
section 14.2.9, Bit Rate Register (SCBRR).
Bit 1: CKS1
Bit 0: CKS0
Description
0
0
Pφ clock
1
Pφ/4 clock
(Initial value)
1
Note:
0
Pφ/16 clock
1
Pφ/64 clock
Pφ (SCI) is a clock scaled from the CKP peripheral clock according to the setting in the
module clock control register. For details see section 4, Clock Pulse Generator (CPG) and
Power-Down Modes.
14.2.6 Serial Control Register (SCSCR)
Bit:
7
6
5
TIE
RIE
TE
Initial value:
0
0
0
R/W: R/W
R/W
R/W
4
3
2
1
0
RE
MPIE TEIE CKE1 CKE0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
The serial control register (SCSCR) performs enabling or disabling of SCI transmit/receive
operations, and interrupt requests, and selection of the transmit/receive clock source.
SCSCR can be read or written to by the CPU at all times.
Rev. 5.00 Sep 11, 2006 page 527 of 916
REJ09B0332-0500