SH7065 Datasheet, PDF (735/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 18 I/O Ports (I/O)
18.5.3 Port D Data Register L (PDDRL)
Bit: 15
14
13
12
11
10
9
PD15DR PD14DR PD13DR PD12DR PD11DR PD10DR PD9DR
Initial value:
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
8
PD8DR
0
R/W
Bit:
Initial value:
R/W:
7
PD7DR
0
R/W
6
PD6DR
0
R/W
5
PD5DR
0
R/W
4
PD4DR
0
R/W
3
PD3DR
0
R/W
2
PD2DR
0
R/W
1
PD1DR
0
R/W
0
PD0DR
0
R/W
Port D data register L (PDDRL) is a 16-bit readable/writable register that stores port D data. Bits
PD15DR to PD0DR correspond to pins PD15/D15/TIOC5B to PD0/D0.
When a pin functions as a general output, if a value is written to PDDRL, that value is output
directly from the pin, and if PDDRL is read, the register value is returned directly regardless of the
pin state.
When a pin functions as a general input, if PDDRL is read the pin state, not the register value, is
returned directly. If a value is written to PDDRL, although that value is written into PDDRL it
does not affect the pin state. Table 18.8 summarizes port D data register read/write operations.
PDDRL is initialized by an external power-on reset, but is not initialized by a WDT reset or in
standby mode or sleep mode.
Table 18.8 Port D Data Register (PDDR) Read/Write Operations
PDIOR
0
1
Pin Function
General input
Read
Pin state
Other than general
input
General output
Other than general
output
Undefined
PDDR value
PDDR value
Write
Value is written to PDDR, but does not
affect pin state
Value is written to PDDR, but does not
affect pin state
Write value is output from pin
Value is written to PDDR, but does not
affect pin state
Rev. 5.00 Sep 11, 2006 page 713 of 916
REJ09B0332-0500