SH7065 Datasheet, PDF (593/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 14 Serial Communication Interface (SCI)
Initialization
1
Start of transmission
Read TDFE bit in SC1SSR
2
TDFE = 1?
No
Yes
Write {16 – (transmit trigger set
number)} bytes of transmit data
to SCFTDR, and set MPBT
in SC1SSR
Clear TDFE and TEND flags to 0
End of transmission?
Yes
No
3
Read TEND bit in SC1SSR
TEND = 1?
Yes
Break output?
Yes
Clear DR to 0
No
No
4
Clear TE bit to 0 in SCSCR,
and set TxD pin as output port
with PFC
End of transmission
1. SCI initialization:
See figure 14.4, Sample SCI
Initialization Flowchart.
2. SCI status check and transmit data
write:
First, set the MPBT bit in SC1SSR to 0
or 1.
Read the serial status 1 register
(SC1SSR) and check that the TDFE bit
is set to 1, then write transmit data to
the transmit FIFO data register
(SCFTDR). Finally, clear the TDFE and
TEND flags to 0 after reading 1 from
them.
The number of data bytes that can be
written is {16 – (transmit trigger set
number)}.
3. Serial transmission continuation
procedure:
To continue serial transmission, read 1
from the TDFE bit to confirm that
writing is possible, then write data to
SCFTDR, and then clear the TDFE bit
to 0. (Checking and clearing of the
TDFE bit is automatic when the DMAC
is activated by a transmit-FIFO-data-
empty interrupt (TXI) request, and data
is written to SCFTDR.)
4. Break output at the end of serial
transmission:
To output a break in serial
transmission, clear the port data
register (DR) to 0, then clear the TE bit
to 0 in SCSCR, and set the TxD pin as
an output port with the PFC.
In steps 2 and 3, the number of transmit
data bytes that can be written can be
ascertained from the number of transmit
data bytes in SCFTDR indicated in the
upper 8 bits of the FIFO data count register
(SCFDR).
Figure 14.11 Sample Multiprocessor Serial Transmission Flowchart
Rev. 5.00 Sep 11, 2006 page 571 of 916
REJ09B0332-0500