SH7065 Datasheet, PDF (289/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 8 Bus State Controller (BSC)
8.3.4 DRAM Interface
Direct Connection of DRAM
When area 4 or area 5 space is accessed, the target space is 64-Mbyte DRAM space, and the
DRAM interface function can then be used to connect DRAM directly to the SH7065.
As CAS is used to control byte access, 2-CAS type 16-bit-width DRAMs can be connected.
In addition to normal read and write access modes, fast page mode is supported for burst access.
EDO mode is similarly supported, enabling one-cycle access in burst mode, in particular.
Address Multiplexing
Address multiplexing is always performed in accesses to DRAM. This enables DRAM, which
requires row and column address multiplexing, to be connected directly to the SH7065 without
using an external address multiplexer circuit. Any of the eight multiplexing methods shown below
can be selected, by setting bits AMX2 to AMX0 in DCR3. The relationship between bits AMX2
to AMX0 and address multiplexing is shown in table 8.10. The address output pins subject to
address multiplexing are A15 to A0. The original address signals are output to pins A25 to A16.
Rev. 5.00 Sep 11, 2006 page 267 of 916
REJ09B0332-0500