SH7065 Datasheet, PDF (359/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 9 Direct Memory Access Controller (DMAC)
In dual address mode, data is read from the transfer source in the data read cycle, and written to
the transfer destination in the data write cycle, so that the transfer is executed in two bus cycles.
The transfer data is temporarily stored in the DMAC. In a transfer between external memories
such as that shown in figure 9.7, data is read from external memory into the DMAC in the read
cycle, then written to the other external memory in the write cycle. Figure 9.8 shows the timing for
this operation.
DMAC
SAR
DAR
Memory
Transfer source
module
Data buffer
Transfer destination
module
Taking the SAR value as the address, data is read from the transfer source module
and stored temporarily in the data buffer in the DMAC.
First bus cycle
DMAC
SAR
DAR
Memory
Transfer source
module
Data buffer
Transfer destination
module
Taking the DAR value as the address, the data stored in the DMAC is written to
the transfer destination module.
Second bus cycle
Figure 9.7 Direct Address Operation in Dual Address Mode
Rev. 5.00 Sep 11, 2006 page 337 of 916
REJ09B0332-0500