SH7065 Datasheet, PDF (517/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 12 Compare Match Timer (CMT)
12.1.3 Register Configuration
Table 12.1 summarizes the CMT registers.
Table 12.1 CMT Registers
Channel Name
Abbre-
viation
Initial
R/W Value Address
Access
Size
Both
0
Compare match timer start
register
Compare match timer
control/status register 0
CMSTR
CMCSR0
R/W H'0000
R/(W)^* H'0000
H'FFFF04C0 8, 16, 32
H'FFFF04C2 8, 16, 32
Compare match timer
counter 0
CMCNT0 R/W H'0000 H'FFFF04C4 8, 16, 32
Compare match timer
constant register 0
CMCOR0 R/W H'FFFF H'FFFF04C6 8, 16, 32
1
Compare match timer
CMCSR1 R/(W)^* H'0000 H'FFFF04C8 8, 16, 32
control/status register 1
Compare match timer
counter 1
CMCNT1 R/W H'0000 H'FFFF04CA 8, 16, 32
Compare match timer
constant register 1
CMCOR1 R/W H'FFFF H'FFFF04CC 8, 16, 32
Note: * The CMF bit in CMCSR0 and CMCSR1 can only be written with 0, to clear the flag.
Rev. 5.00 Sep 11, 2006 page 495 of 916
REJ09B0332-0500