SH7065 Datasheet, PDF (269/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 8 Bus State Controller (BSC)
8.2.10 Refresh Count Register (RFCR)
The refresh count register (RFCR) is a 12-bit readable/writable counter that counts the number of
refreshes by being incremented each time the RTCOR register and RTCNT counter values match.
If the RFCR register value exceeds the count limit specified by bits LMTS1 and LMTS0 in the
RTCSR register, the OVF flag is set in the RTCSR register and the RFCR register is cleared.
RFCR bits 15 to 12 are reserved; they are always read as 0 and should only be written with 0.
RFCR is initialized to H'0000 by a power-on reset. In standby mode, RFCR is not initialized, and
retains its contents.
Bit: 15
14
13
12
11
10
9
8
—
—
—
— RFCR11 RFCR10 RFCR9 RFCR8
Initial value:
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
7
RFCR7
0
R/W
6
RFCR6
0
R/W
5
RFCR5
0
R/W
4
RFCR4
0
R/W
3
RFCR3
0
R/W
2
RFCR2
0
R/W
1
RFCR1
0
R/W
0
RFCR0
0
R/W
Rev. 5.00 Sep 11, 2006 page 247 of 916
REJ09B0332-0500