SH7065 Datasheet, PDF (190/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 5 Exception Handling
5.3 Address Errors
5.3.1 Address Error Sources
Address errors occur in instruction fetches and data read/write accesses, as shown in table 5.5.
Table 5.5 Bus Cycles and Address Errors
Type
Bus Cycle
Bus Master Bus Cycle Operation
Address Error
Occurrence
Instruction
fetch
CPU
Instruction fetched from even address
Instruction fetched from odd address
No error (normal)
Address error
Instruction fetched from other than on-chip No error (normal)
peripheral module space^*
Instruction fetched from on-chip peripheral Address error
module space^*
Instruction fetched from external memory
space in single-chip mode
Address error
Data
read/write
CPU or
DMAC
Word data accessed from even address
Word data accessed from odd address
No error (normal)
Address error
Longword data accessed from longword
boundary
No error (normal)
Longword data accessed from other than
longword boundary
Address error
Word data or byte data accessed in on-chip No error (normal)
peripheral module space^*
Longword data accessed in 16-bit on-chip
peripheral module space^*
No error (normal)
Longword data accessed in 8-bit on-chip
peripheral module space^*
No error (normal)
External memory space accessed in single- Address error
chip mode
Note: * For details of the on-chip peripheral module space, see section 8, Bus State Controller
(BSC).
Rev. 5.00 Sep 11, 2006 page 168 of 916
REJ09B0332-0500