SH7065 Datasheet, PDF (635/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 15 A/D Converter
15.4.2 Multi Mode
Multi mode is useful for monitoring analog inputs in a group of one or more channels. When the
ADST bit in the A/D control/status register (ADCSR) is set to 1 by software or external trigger
input, A/D conversion starts on the first channel in the group (AN0 in A/D0, or AN4 in A/D1).
When more than one channel has been selected, A/D conversion starts on the second channel
(AN1 or AN5) as soon as conversion ends on the first channel.
After A/D conversion has been performed once on each of the selected channels, the ADST bit is
cleared to 0 automatically. The conversion results are transferred to and stored in the ADDR
register for each channel.
To prevent incorrect operation, A/D conversion should be halted by clearing the ADST bit to 0
before changing the mode or analog input channels. After the change is made, the first channel is
selected and A/D conversion is restarted by setting the ADST bit to 1 (the mode or channel change
and setting of the ADST bit can be carried out simultaneously).
An example of the A/D conversion operation in multi mode when three channels (AN0 to AN2) in
group 0 are selected is described below. Figure 15.4 shows a timing diagram for this example (bit
specifications in the operation example refer to the ADCSR0 register).
1. Multi mode is selected (MULTI = 1), analog input channels AN0 to AN2 are selected (CH1 =
1, CH0 = 0), and A/D conversion is started (ADST = 1).
2. A/D conversion starts on the first channel (AN0), and when completed, the result is transferred
to ADDRA0. Conversion then starts automatically on the second channel (AN1).
3. Conversion proceeds in the same way through the third channel (AN2).
4. When conversion is completed for all the selected channels (AN0 to AN2), ADF is set to 1
ADST is cleared to 0, and conversion stops.
If the ADIE bit is 1, an ADI interrupt is requested when conversion ends.
When the ADST bit is cleared to 0, A/D conversion stops.
5. ADF is read while set to 1, then written with 0. After this, if the ADST bit is set to 1, A/D
conversion starts again from the first channel (AN0).
Rev. 5.00 Sep 11, 2006 page 613 of 916
REJ09B0332-0500