SH7065 Datasheet, PDF (194/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 5 Exception Handling
5.5.3 Slot Illegal Instructions
An instruction located immediately after a delayed branch instruction is said to be located in the
delay slot. If the instruction in the delay slot is undefined code, slot illegal instruction exception
handling is started when that undefined code is decoded. Also, if the instruction in the delay slot is
one that modifies the program counter (PC), slot illegal instruction exception handling is started
when that instruction is decoded. CPU operations in slot illegal instruction exception handling are
as follows.
1. The status register (SR) is saved on the stack.
2. The program counter (PC) is saved on the stack. The PC value saved is the jump destination
address of the delayed branch instruction immediately preceding the undefined code or PC-
modifying instruction.
3. The exception service routine start address is fetched from the exception vector table entry
corresponding to the generated exception, a jump is made to that address, and program
execution starts from that point. The jump in this case is not a delayed branch.
5.5.4 General Illegal Instructions
When undefined code located other than immediately after a delayed branch instruction (in a delay
slot) is decoded, general illegal instruction exception handling is started. The CPU follows the
same procedure as in the case of slot illegal instruction exception handling, except that the
program counter (PC) value saved is the start address of the undefined code.
Rev. 5.00 Sep 11, 2006 page 172 of 916
REJ09B0332-0500