SH7065 Datasheet, PDF (223/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

6.7 Usage Notes
Section 6 Interrupt Controller (INTC)
6.7.1
IRQ3 to IRQ0 Sampling and Interrupt Source Determination in IRL Interrupt
Mode
Low level sensing or falling edge sensing can be set as the sampling method for each of pins IRQ3
to IRQ0 by means of IRQ sense select bits 3 to 0 in interrupt control register 2 (ICR2).
In IRL interrupt mode, the same sampling method must be set for all four pins, IRQ3 to IRQ0.
When low level sensing is set for IRQ3 to IRQ0, on acceptance of an interrupt request the
interrupt source (IRL1 to IRL15) is determined by the levels of IRQ3 to IRQ0.
When falling edge sensing is set for IRQ3 to IRQ0, the falling edge detection results for IRQ3 to
IRQ0 are retained. When an interrupt request is accepted, the interrupt source (IRL1 to IRL15) is
determined by the retained detection results.
For example, if level 3 (IRQ[3:0] = H'1100) input is not accepted, and this is followed by level 4
(IRQ[3:0] = H'1011) input without clearing the retained detection results, a level 7 (IRQ[3:0] =
H'1000) interrupt request will be judged to have been issued on the basis of the detection results
retained up to that point. In this example, in order to end up with a level 4 interrupt request, the
level 3 detection results must be cleared before the level 4 interrupt signal is input. Detection
results can be cleared by reading 1 from bits IRQ3F to IRQ0F in the IRQ status register (ISR),
then writing 0 to these bits.
6.7.2 IRQ Pin Noise Cancellation Function
Signals IRQ7 to IRQ0 are sent to the interrupt controller via a noise canceler that eliminates noise
of one state or less in duration. Therefore, when edge detection is set for the IRQ pins, the IRQ
input must be at least 2.5 states in duration.
Rev. 5.00 Sep 11, 2006 page 201 of 916
REJ09B0332-0500