SH7065 Datasheet, PDF (335/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 9 Direct Memory Access Controller (DMAC)
9.2.4 DMA Channel Control Registers 0 to 3 (CHCR0 to CHCR3)
Bit: 31
30
29
28
27
26
25
24
—
—
—
RS4
RS3
RS2
RS1
RS0
Initial value:
0
0
0
0
0
0
0
0
R/W: R
R
R
R/W
R/W
R/W
R/W
R/W
Bit: 23
22
21
—
FIFOS
—
Initial value:
0
0
0
R/W: R
R/W
R
20
19
18
17
— NDARE NSARE FCS
0
0
0
0
R
R/W
R/W
R/W
16
TES
0
R/W
Bit: 15
14
13
12
11
10
9
8
DM1
DM0
SM1
SM0 CHNE
RL
AM
AL
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
TEND DS
TM
TS1
TS0
IE
TE^*
DE
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: * The TE bit can only be cleared by writing 0 after it is read as 1.
DMA channel control registers 0 to 3 (CHCR0 to CHCR3) are 32-bit readable/writable registers
that specify the operating mode, transfer method, etc., for each channel.
All bits in these registers are initialized to 0 after a power-on reset, and in hardware standby mode
and software standby mode.
Bits 31 to 29—Reserved: These bits are always read as 0 and cannot be modified.
Rev. 5.00 Sep 11, 2006 page 313 of 916
REJ09B0332-0500