SH7065 Datasheet, PDF (65/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

2.4 Instruction Formats
Section 2 CPU
2.4.1 CPU Instruction Addressing Modes
The following table shows addressing modes and effective address calculation methods for
instructions executed by the CPU core.
Table 2.12 Addressing Modes and Effective Addresses for CPU Instructions
Addressing
Mode
Register
direct
Register
indirect
Instruction
Format
Rn
@Rn
Effective Address Calculation Method
Effective address is register Rn.
(Operand is register Rn contents.)
Effective address is register Rn contents.
Rn
Rn
Calculation
Formula
—
Rn
Register
indirect
with post-
increment
@Rn+
Effective address is register Rn contents.
A constant is added to Rn after instruction
execution: 1 for a byte operand, 2 for a word
operand, 4 for a longword operand.
Rn
Rn
Rn + 1/2/4 ₊
Rn
After instruction
execution
Byte: Rn + 1 → Rn
Word: Rn + 2 → Rn
Longword:
Rn + 4 → Rn
1/2/4
Register
indirect
with pre-
decrement
@-Rn
Effective address is register Rn contents,
decremented by a constant beforehand:
1 for a byte operand, 2 for a word operand,
4 for a longword operand.
Rn
Rn – 1/2/4 _–
Rn – 1/2/4
Byte: Rn – 1 → Rn
Word: Rn – 2 → Rn
Longword:
Rn – 4 → Rn
(Instruction
executed with Rn
after calculation)
1/2/4
Rev. 5.00 Sep 11, 2006 page 43 of 916
REJ09B0332-0500