SH7065 Datasheet, PDF (263/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 8 Bus State Controller (BSC)
Bits 12 and 11—Bus Width Specification (DSZ1, DSZ0): These bits specify the bus width for
DRAM.
Bit 12: DSZ1
0
1
Bit 11: DSZ0
0
1
0
1
Description
Reserved (Do not set)
8 bits
16 bits
32 bits
(Initial value)
Bits 10 to 8—Address Multiplexing Specification (AMX2 to AMX0): These bits specify
DRAM address multiplexing.
Bit 10: AMX2
0
1
Bit 9: AMX1
0
1
0
1
Bit 8: AMX0
0
1
0
1
0
1
0
1
Description
9 bits
10 bits
11 bits
12 bits
13 bits
14 bits
15 bits
16 bits
(Initial value)
Bit 7—Refresh Control (RFSH): Specifies whether or not refreshing is performed for DRAM.
When the refresh function is not used, the refresh request cycle generation timer can be used as an
interval timer.
Bit 7: RFSH
0
1
Description
Refreshing is not performed
Refreshing is performed
(Initial value)
Bit 6—Refresh Mode (RMD): Specifies whether normal refreshing or self-refreshing is
performed for DRAM when the RFSH bit is set to 1. When the RFSH bit is 1 and this bit is
cleared to 0, CAS-before-RAS refreshing is performed using the cycle set with refresh-related
registers RTCNT, RTCOR, and RTCSR. If a refresh request is issued during execution of an
external bus cycle, the refresh cycle is executed when the bus cycle ends. When the RFSH bit is 1
and this bit is set to 1, the self-refresh state is set after waiting for the end of any currently
executing external bus cycle. All refresh requests for memory in the self-refresh state are ignored.
Rev. 5.00 Sep 11, 2006 page 241 of 916
REJ09B0332-0500