SH7065 Datasheet, PDF (211/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 6 Interrupt Controller (INTC)
Table 6.7 Interrupt Request Sources and Registers IPRA to IPRL
Register
Interrupt priority register A
Interrupt priority register B
Interrupt priority register C
Interrupt priority register D
Interrupt priority register E
Interrupt priority register F
Interrupt priority register G
Interrupt priority register H
Interrupt priority register I
Interrupt priority register J
Interrupt priority register K
Interrupt priority register L
15–12
IRQ0
IRQ4
Reserved
Reserved
DMAC0
Reserved
BSC
TPU0
TPU2
TPU4
SCI0
CMT
11–8
IRQ1
IRQ5
Reserved
Reserved
DMAC1
Reserved
BSC
TPU0
TPU2
TPU4
SCI1
A/D
Bits
7–4
IRQ2
IRQ6
Reserved
Reserved
DMAC2
Reserved
WDT
TPU1
TPU3
TPU5
SCI2
MMT
3–0
IRQ3
IRQ7
Reserved
Reserved
DMAC3
Reserved
Reserved
TPU1
TPU3
TPU5
Reserved
POE (I/O)
Four IRQ pins or four on-chip peripheral modules are assigned to one register. Interrupt priority
levels are established by setting a value from H'0 (0000) to H'F (1111) in each of the four-bit
groups: 15 to 12, 11 to 8, 7 to 4, and 3 to 0. Setting H'0 designates priority level 0 (the lowest
level), and setting H'F designates priority level 15 (the highest level).
Registers IPRA to IPRL are initialized to H'0000 by a power-on reset. They are not initialized in
standby mode. Reserved bits are always read as 0, and should only be written with 0.
Rev. 5.00 Sep 11, 2006 page 189 of 916
REJ09B0332-0500