SH7065 Datasheet, PDF (86/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 2 CPU
Type
Arithmetic
operation
instructions
Kinds of
Instruction
21
Op Code
EXTS
EXTU
MAC
Logic operation 6
instructions
Shift
10
instructions
MUL
MULS
MULU
NEG
NEGC
SUB
SUBC
SUBV
AND
NOT
OR
TAS
TST
XOR
ROTCL
ROTCR
ROTL
ROTR
SHAL
SHAR
SHLL
SHLLn
SHLR
SHLRn
Function
Number of
Instructions
Sign extension
33
Zero extension
Multiply and accumulate, double-
precision multiply and accumulate
Double-precision multiplication
Signed multiplication
Unsigned multiplication
Sign inversion
Sign inversion with borrow
Binary subtraction
Binary subtraction with borrow
Binary subtraction with underflow
Logical AND
14
Bit inversion
Logical OR
Memory test and bit set
Logical AND T bit state
Exclusive logical OR
1-bit left shift with T bit
14
1-bit right shift with T bit
1-bit left shift
1-bit right shift
Arithmetic 1-bit left shift
Arithmetic 1-bit right shift
Logical 1-bit left shift
Logical n-bit left shift
Logical 1-bit right shift
Logical n-bit right shift
Rev. 5.00 Sep 11, 2006 page 64 of 916
REJ09B0332-0500