SH7065 Datasheet, PDF (245/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Name
Output enable
Address hold
Wait
Bus release
request
Bus request
acknowledge
Signals
OE1, OE0
AH
WAIT
BREQ
BACK
I/O
Output
Output
Input
Input
Section 8 Bus State Controller (BSC)
Function
Output enable signals for EDO DRAM connected to
areas 5 and 4. Used for access in RAS down
mode.
Signal for holding address in address/data
multiplexing
Wait state request signal
Bus release request signal
Output Signal granting use of the bus
Rev. 5.00 Sep 11, 2006 page 223 of 916
REJ09B0332-0500