SH7065 Datasheet, PDF (235/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 7 User Break Controller (UBC)
7.3.4 X Memory Bus or Y Memory Bus Cycle Break
When XYE is set to 1 in UBBR, break addresses on the X memory bus or Y memory bus are
selected. Either the X memory bus or the Y memory bus must be selected with the XYS bit in
UBBR; the X and Y memory buses cannot both be included in the break conditions at the same
time. The break conditions are applied to X memory bus cycles or Y memory bus cycles by
specifying the CPU bus master, data access cycle, read or write access, and word operand size or
operand size not included.
When the X memory address bus is selected as a break condition, specify the X memory address
in UBARH and UBAMRH; when the Y memory address bus is selected, specify the Y memory
address in UBARL and UBAMRL.
7.3.5 Program Counter (PC) Value Saved
When Instruction Fetch is Set as User Break Condition
The program counter (PC) value saved in user break interrupt exception handling is the address of
the instruction to be executed after the instruction at which the user break condition was satisfied.
The instruction at which the break condition was satisfied is executed, and a user break interrupt is
generated before execution of the next instruction. However, when a user break condition is set for
a delayed branch instruction, the delay slot instruction is executed, and the user break interrupt is
generated before execution of the branch instruction. In this case, the PC value is the address of
the branch destination instruction.
When Data Access (CPU/DMA) is Set as User Break Condition
The address saved is the start address of the instruction following the instruction for which
execution has been completed at the point at which user break exception handling starts. When a
data access (CPU/DMA) is set as a user break condition, it is not possible to specify where the
break will occur. The break will be effected at an instruction about to be fetched close to where the
break data access occurred.
Rev. 5.00 Sep 11, 2006 page 213 of 916
REJ09B0332-0500