SH7065 Datasheet, PDF (699/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 17 Pin Function Controller (PFC)
Bits 3 and 2—PD17 Mode 1 and 0 (PD17MD1, PD17MD0): These bits select the function of
the PD17/D17/POE1/ADTRG pin.
Bit 3: PD17MD1
0
1
Bit 2: PD17MD0
0
1
0
1
Description
General input/output (PD17)
(Initial value)
(D17 in on-chip ROM disabled modes with 32-bit CS0
bus width)
Data input/output (D17) (PD17 in single-chip mode)
MMT port output enable input (POE1)
A/D conversion trigger input (ADTRG)
Bits 1 and 0—PD16 Mode 1 and 0 (PD16MD1, PD16MD0): These bits select the function of
the PD16/D16/POE0 pin.
Bit 1: PD16MD1
0
1
Bit 0: PD16MD0
0
1
0
1
Description
General input/output (PD16)
(Initial value)
(D16 in on-chip ROM disabled modes with 32-bit CS0
bus width)
Data input/output (D16) (PD16 in single-chip mode)
MMT port output enable input (POE0)
Reserved (Do not set)
17.3.16 Port D Control Registers L1 and L2 (PDCRL1, PDCRL2)
Port D control registers L1 and L2 (PDCRL1, PDCRL2) are 16-bit readable/writable registers that
select the functions of pins in port D.
PDCRL1 selects the functions of port D pins PD15/D15/TIOC5B to PD8/D8/TIOC1A, and
PDCRL2 selects the functions of port D pins PD7/D7 to PD0/D0.
Port D includes data input/output functions (D0 to D15), but register settings relating to the
selection of these pin functions may not be valid in all operating modes. For details, see table
17.10, Pin Functions in Each Operating Mode.
PDCRL1 and PDCRL2 are initialized to H'0000 by an external power-on reset, but are not
initialized by a WDT reset, in standby mode, or in sleep mode.
Rev. 5.00 Sep 11, 2006 page 677 of 916
REJ09B0332-0500