SH7065 Datasheet, PDF (767/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Automatic SCI Bit Rate Adjustment
Section 19 256 kB Flash Memory (F-ZTAT)
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
Stop
bit
Low period (9 bits) measured (H'00 data)
High period
(1 or more bits)
Figure 19.10 Automatic SCI Bit Rate Adjustment
When boot mode is initiated, the SH7065 measures the low period of the asynchronous SCI
communication data (H'00) transmitted continuously from the host. The SCI transmit/receive
format should be set as follows: 8-bit data, 1 stop bit, no parity. The SH7065 calculates the bit rate
of the transmission from the host from the measured low period, and transmits one H'00 byte to
the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end
indication (H'00) has been received normally, and transmit one H'55 byte to the SH7065. If
reception cannot be performed normally, initiate boot mode again (reset), and repeat the above
operations.
Table 19.7 shows host transfer bit rates and peripheral clock frequencies for which automatic
adjustment of the SH7065 bit rate is possible. The boot program should set the initial settings for
the clock division ratios (in clock mode 7 only, the peripheral clock is set to 1/2 the input), no
module clock division, and 4 times the bit rate for the SCI2 base clock. The boot program should
be executed with a bit rate for which adjustment is possible according to the peripheral clock
frequency.
Table 19.7 Peripheral Clock Frequencies Enabling Automatic Adjustment of SH7065 Bit
Rate
Host Bit Rate
19200 bps
9600 bps
Peripheral Clock Frequency Enabling Automatic Adjustment
of SH7065 Bit Rate
4–30 MHz
2–30 MHz
Rev. 5.00 Sep 11, 2006 page 745 of 916
REJ09B0332-0500