SH7065 Datasheet, PDF (210/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 6 Interrupt Controller (INTC)
Interrupt Source
A/D
ADI0
ADI1
Reserved
Reserved
MMT
TGIM
TGIN
Reserved
Reserved
POE (I/O) OEI
Reserved
Reserved
Reserved
Interrupt
Priority
(Initial
Value)
0–15 (0)
0–15 (0)
0–15 (0)
IPR
(Bit
Numbers)
IPRL (11–8)
IPRL (7–4)
IPRL (3–0)
Priority
within IPR Vector Vector
Setting Number Table Offset
High
208
H'0000 0340
209
H'0000 0344
210
H'0000 0348
Low
211
H'0000 034C
High
212
H'0000 0350
213
H'0000 0354
214
H'0000 0358
Low
215
H'0000 035C
High
216
H'0000 0360
217
H'0000 0364
218
H'0000 0368
Low
219
H'0000 036C
Default
Priority
High
Low
6.3 Register Descriptions
6.3.1 Interrupt Priority Registers A to L (IPRA to IPRL)
Bit: 15
14
13
12
11
10
9
8
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Interrupt priority registers A to L (IPRA to IPRL) are 16-bit readable/writable registers that set
priority levels from 0 to 15 for IRQ interrupts and on-chip peripheral module interrupts. Table 6.7
shows the relationship between the interrupt request sources and bits in registers IPRA to IPRL.
Rev. 5.00 Sep 11, 2006 page 188 of 916
REJ09B0332-0500