SH7065 Datasheet, PDF (198/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 5 Exception Handling
5.8 Usage Notes
5.8.1 Stack Pointer (SP) Value
Ensure that the stack pointer (SP) value is a multiple of 4. If it is not, an address error will be
caused when the stack is accessed in exception handling.
5.8.2 Vector Base Register (VBR) Value
Ensure that the vector base register (VBR) value is a multiple of 4. If it is not, an address error will
be caused when the stack is accessed in exception handling.
5.8.3 Address Errors Occurring in Address Error Exception Handling Stacking
If the stack pointer (SP) value is not a multiple of 4, an address error will occur in exception
handling (interrupt, etc.) stacking, and after the exception handling is completed, address error
exception handling will be started. An address error will also occur in stacking in the address error
exception handling, but this address error will not be accepted in order to prevent endless stacking
due to address errors. This enables program control to be switched to the address error exception
service routine, and error handling to be carried out.
When an address error occurs in exception handling stacking, the stacking bus cycle (write) is
executed. In status register (SR) and program counter (PC) stacking, SP is decremented by 4 in
each case, and therefore the SP value is not a multiple of 4 after stacking is completed. Also, the
address value output in stacking is the SP value, and the actual address at which the error occurred
is output. In this case, the stacked write data is undefined.
Rev. 5.00 Sep 11, 2006 page 176 of 916
REJ09B0332-0500