SH7065 Datasheet, PDF (444/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
Examples of Cascaded Operation
Figure 10.22 illustrates the operation when counting upon TCNT2 overflow/underflow has been
set for TCNT1, and phase counting mode has been designated for channel 2.
TCNT1 is incremented by TCNT2 overflow and decremented by TCNT2 underflow.
TCLKA
TCLKB
TCNT2
FFFD FFFE FFFF 0000 0001
0002
0001 0000 FFFF
TCNT1
0000
0001
0000
Figure 10.22 Example of Cascaded Operation
10.4.6 PWM Modes
In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be
selected as the output level in response to compare match of each TGR.
Designating TGR compare match as the counter clearing source enables the cycle to be set in that
register. All channels can be designated for PWM mode independently. Synchronous operation is
also possible.
There are two PWM modes, as described below.
• PWM mode 1
PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and
TGRC with TGRD. The output specified by TIOR bits IOA3 to IOA0 or IOC3 to IOC0 is
performed from the TIOCA or TIOCC pin upon compare match A or C. Also, the output
specified by TIOR bits IOB3 to IOB0 or IOD3 to IOD0 is performed upon compare match B
or D. The initial output value is the value set in TGRA or TGRC. If the set values of the paired
TGR registers are identical, the output value does not change when a compare match occurs.
In PWM mode 1, a maximum 8-phase PWM output is possible.
Rev. 5.00 Sep 11, 2006 page 422 of 916
REJ09B0332-0500