SH7065 Datasheet, PDF (620/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 14 Serial Communication Interface (SCI)
When Using Synchronous External Clock Mode
• Do not set TE or RE to 1 until at least 4 peripheral operating clock cycles after external clock
SCK has changed from 0 to 1.
• Only set both TE and RE to 1 when external clock SCK is 1.
• In reception, note that if RE is cleared to 0 from 2.3 to 3.5 peripheral operating clock cycles
after the rising edge of the RxD D7 bit SCK input, RDF will be set to 1 but copying to
SCFRDR will not be possible.
When Using Synchronous Internal Clock Mode
In reception, note that if RE is cleared to 0 1.5 peripheral operating clock cycles after the rising
edge of the RxD D7 bit SCK output, RDF will be set to 1 but copying to SCFRDR will not be
possible.
When Using the DMAC
When an external clock source is used as the serial clock, the transmit clock should not be input
until at least 5 Pφ clock cycles after SCFTDR is updated by the DMAC. Incorrect operation may
result if the transmit clock is input within 4 Pφ cycles after SCFTDR is updated. (See figure
14.27.)
When performing SCFRDR reads by the DMAC, be sure to set the relevant SCI receive-FIFO-
data-full interrupt (RXI) as an activation source.
Also, it is recommended that the FCS bit be set to 1 (flag clearing performed every bus cycle) and
the DS bit be set to 1 (falling edge detection) in the DMAC’s CHCRn register, as in section 9.4.1,
Example of DMA Transfer between On-Chip SCI and External Memory.
SCK
t
TDFE
TXD
D0
D1
D2
D3
D4
D5
D6
Figure 14.27 Example of Synchronous Transmission by DMAC
Rev. 5.00 Sep 11, 2006 page 598 of 916
REJ09B0332-0500