SH7065 Datasheet, PDF (524/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 12 Compare Match Timer (CMT)
12.4.3 Timing of Compare Match Flag Clearing
The CMF bit in CMCSR is cleared by reading the bit when it is set to 1, then writing 0 to it.
Figure 12.5 shows the timing of CMF bit clearing.
CMCSR write cycle
T1 T2
Pφ
CMF
Figure 12.5 Timing of CMF Clearing
12.5 Usage Notes
Note that the kinds of operation and contention described below occur during CMT operation.
Contention between CMCNT Write and Compare Match
If a compare match occurs in the T2 state of a CMCNT write cycle, the CMCNT clearing takes
precedence and the write to CMCNT is not performed.
Figure 12.6 shows the timing in this case.
Pφ
Address
CMCNT write cycle
T1 T2
CMCNT
Internal write signal
Counter clear signal
CMCNT
N
H'0000
Figure 12.6 Contention between CMCNT Write and Compare Match
Rev. 5.00 Sep 11, 2006 page 502 of 916
REJ09B0332-0500