SH7065 Datasheet, PDF (457/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.13 lists the TPU interrupt sources.
Table 10.13 TPU Interrupts
Interrupt
Channel Source
Description
DMAC
Activation
Priority
0
TGI0A
TGR0A input capture/compare match
Possible
High
TGI0B
TGR0B input capture/compare match
Not possible
TGI0C
TGR0C input capture/compare match
Not possible
TGI0D
TGR0D input capture/compare match
Not possible
TCI0V
TCNT0 overflow
Not possible
1
TGI1A
TGR1A input capture/compare match
Possible
TGI1B
TGR1B input capture/compare match
Not possible
TCI1V
TCNT1 overflow
Not possible
TCI1U
TCNT1 underflow
Not possible
2
TGI2A
TGR2A input capture/compare match
Possible
TGI2B
TGR2B input capture/compare match
Not possible
TCI2V
TCNT2 overflow
Not possible
TCI2U
TCNT2 underflow
Not possible
3
TGI3A
TGR3A input capture/compare match
Possible
TGI3B
TGR3B input capture/compare match
Not possible
TGI3C
TGR3C input capture/compare match
Not possible
TGI3D
TGR3D input capture/compare match
Not possible
TCI3V
TCNT3 overflow
Not possible
4
TGI4A
TGR4A input capture/compare match
Possible
TGI4B
TGR4B input capture/compare match
Not possible
TCI4V
TCNT4 overflow
Not possible
TCI4U
TCNT4 underflow
Not possible
5
TGI5A
TGR5A input capture/compare match
Possible
TGI5B
TGR5B input capture/compare match
Not possible
TCI5V
TCNT5 overflow
Not possible
TCI5U
TCNT5 underflow
Not possible Low
Note: This table shows the initial state immediately after a reset. The relative channel priorities
can be changed by the interrupt controller.
Rev. 5.00 Sep 11, 2006 page 435 of 916
REJ09B0332-0500