SH7065 Datasheet, PDF (494/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 11 Motor Management Timer (MMT)
Register Updating
In the operating modes, buffer registers are used to update compare register data. Update data can
be written to a buffer register at all times. The buffer register value is transferred to the compare
register at the timing set by bits MD1 and MD0 in the timer mode register (TMDR) (except in the
case of a write to the free operation address for TBRU to TBRW, in which case the value is
transferred to the compare register immediately).
Initial Output in Operating Modes
The initial output in the operating modes is determined by the initial value of TBRU to TBRW.
Table 11.4 shows the relationship between the initial value of TBRU to TBRW and the initial
output.
Table 11.4 Initial Values of TBRU to TBRW and Initial Output
Initial Value of TBRU to TBRW
TBR = H'0000
H'0000 < TBR ≤ Td
Td < TBR ≤ H'FFFF – 2Td
Initial Output
OLSP = 1, OLSN = 1
OLSP = 0, OLSN = 0
Positive phase: 1
Positive phase: 0
Negative phase: 0
Negative phase: 1
Positive phase: 0
Positive phase: 1
Negative phase: 0
Negative phase: 1
Positive phase: 0
Positive phase: 1
Negative phase: 1
Negative phase: 0
PWM Output Generation in Operating Modes
In the operating modes, 3-phase PWM waveform output is performed with a non-overlap
relationship between the positive and negative phases. This non-overlap time is called the dead
time.
The PWM waveform is generated from an output generation waveform generated by ANDing the
compare output waveform with the dead time generation waveform. Waveform generation for one
phase (the U-phase) is shown here. The V-phase and W-phase waveforms are generated in the
same way.
Rev. 5.00 Sep 11, 2006 page 472 of 916
REJ09B0332-0500