SH7065 Datasheet, PDF (711/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 17 Pin Function Controller (PFC)
Port F IO register L (PFIORL) is a 16-bit readable/writable register that selects the input/output
direction of pins in port F. Bits PF7IOR to PF1IOR correspond to pins
PF7/DREQ1/IRQOUT/TIOC0D to PF1/DACK0/TIOC0B. PFIORL is enabled when port F pins
function as general input/output pins (PF7 to PF1) or TPU TIOC pins, and disabled otherwise.
When port F pins function as PF7 to PF1 or TPU TIOC pins, a pin becomes an output when the
corresponding bit in PFIORL is set to 1, and an input when the bit is cleared to 0.
PFIORL is initialized to H'0000 by an external power-on reset, but is not initialized by a WDT
reset, in standby mode, or in sleep mode.
17.3.22 Port F Control Register L2 (PFCRL2)
Bit: 15
14
13
12
11
10
9
8
PF7
PF7
PF6
PF6
PF5
PF5
—
—
MD1 MD0 MD1 MD0 MD1 MD0
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R
R
Bit:
7
6
5
4
3
2
1
0
PF3
PF3
PF2
PF2
PF1
PF1
—
—
MD1 MD0 MD1 MD0 MD1 MD0
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R
R
Port F control register L2 (PFCRL2) is a 16-bit readable/writable register that selects the functions
of pins in port F.
PFCRL2 selects the functions of port F pins PF7/DREQ1/IRQOUT/TIOC0D to
PF1/DACK0/TIOC0B.
Port F includes DMAC control signals (DREQ0, DREQ1, DRAK0, DRAK1, DACK0, and
DACK1), but register settings relating to the selection of these pin functions may not be valid in
all operating modes. For details, see table 17.10, Pin Functions in Each Operating Mode.
PFCRL2 is initialized to H'0000 by an external power-on reset, but is not initialized by a WDT
reset, in standby mode, or in sleep mode.
Rev. 5.00 Sep 11, 2006 page 689 of 916
REJ09B0332-0500