SH7065 Datasheet, PDF (347/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 9 Direct Memory Access Controller (DMAC)
9.3.1 DMA Transfer Procedure
After the desired transfer conditions have been set in the DMA source address register (SAR),
DMA destination address register (DAR), DMA transfer count register (DMATCR), DMA
channel control register (CHCR), DMA operation register (DMAOR), next source address register
(NSAR), next destination address register (NDAR), next transfer count register (NDMATCR), and
chain transfer count register (CHNCNT), the DMAC executes data transfer according to the
following procedure:
1. The DMAC checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE =
0).
2. When a transfer request is issued while transfer is enabled, the DMAC transfers one transfer
unit of data (determined by the setting of TS0 and TS1). In auto-request mode, the transfer
begins automatically when the DE bit and DME bit are set to 1. The DMATCR value is
decremented by 1 for each transfer. The actual transfer flow depends on the address mode and
bus mode.
3. When the specified number of transfers have been completed (when the DMATCR value
reaches 0), the transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DEI
interrupt request is sent to the CPU.*
4. When a DMAC address error or NMI interrupt occurs, the transfer is suspended. Transfer is
also suspended when the DE bit in CHCR or the DME bit in DMAOR is cleared to 0.
5. In the case of auto-request, or when CHNE = 0 and TES = 1, transfer ends when DMATCRn =
0.
When the chain transfer enable bit (CHNE) is set to 1, the values in the next source address
register (NSAR), next destination address register (NDAR), and next transfer count register
(NDMATCR) are copied, respectively, to the DMA source address register (SAR), DMA
destination address register (DAR), and DMA transfer count register (DMATCR), and chain
transfer is started. Chain transfer ends when the value in the chain transfer count register
(CHNCNT) reaches 0.
Note: * If the TES bit in CHCRn is cleared to 0, a DEI interrupt is generated when the
CHNCNTn and DMATCRn values both become 0.
Figure 9.2 shows a flowchart of this procedure.
Rev. 5.00 Sep 11, 2006 page 325 of 916
REJ09B0332-0500