SH7065 Datasheet, PDF (475/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
Contention between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, TCNT clearing takes
precedence and the TCFV/TCFU flag in TSR is not set.
Figure 10.55 shows the operation timing when a TGR compare match is specified as the clearing
source, and H'FFFF is set in TGR.
Pφ
TCNT input
clock
TCNT
H'FFFF
H'0000
Counter clear
signal
TGF
TCFV
Inhibited
Figure 10.55 Contention between Overflow and Counter Clearing
Rev. 5.00 Sep 11, 2006 page 453 of 916
REJ09B0332-0500