SH7065 Datasheet, PDF (791/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

H'000000
EB0
H'001000
EB1
H'002000
EB2
H'003000
EB3
H'004000
EB4
H'005000
EB5
H'006000
EB6
H'007000
EB7
H'008000
Flash memory
EB8 to EB11
Section 19 256 kB Flash Memory (F-ZTAT)
This area can be accessed
from both the RAM area
and flash memory area
On-chip RAM
On-chip RAM
H'FFFF8000
H'FFFF8FFF
H'FFFFA000
H'FFFFAFFF
H'03FFFF
Figure 19.17 Example of RAM Overlap Operation
Example of Flash Memory Block Area EB1 Overlapping:
1. Set bits RAMAS, RAMS, and RAM2 to RAM0 in RAMER to 0,1, 0, 0, 1, to overlap RAM
(H'FFFF8000 to H'FFFF8FFF) onto the area (EB1) for which real-time programming is
required.
2. Real-time programming is performed using the overlapping RAM.
3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap.
4. The data written in the overlapping RAM is written into the flash memory space (EB1).
Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks
regardless of the value of RAM2 to RAM0 (emulation protection). In this state, setting
the P or E bit in flash memory control register 1 (FLMCR1) will not cause a transition
to program mode or erase mode. When actually programming or erasing a flash
memory area, the RAMS bit should be cleared to 0.
2. A RAM area cannot be erased by execution of software in accordance with the erase
algorithm while flash memory emulation in RAM is being used.
Rev. 5.00 Sep 11, 2006 page 769 of 916
REJ09B0332-0500