SH7065 Datasheet, PDF (413/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
Channel
0
Bit 3:
IOC3
0
1
Legend:
*: Don’t care
Bit 2:
IOC2
0
1
0
1
Bit 1:
IOC1
0
1
0
1
0
1
*
Bit 0:
IOC0
0
1
0
1
0
1
0
1
0
1
*
*
Description
TGR0C is
output
compare
register^*1
Output disabled
(Initial value)
Initial output
is 0 output
0 output at
compare match
1 output at
compare match
Toggle output at
compare match
Output disabled
Initial output
is 1 output
0 output at
compare match
1 output at
compare match
Toggle output at
compare match
TGR0C is Capture input
input capture source is
register^*1
TIOC0C pin
Input capture at
rising edge
Input capture at
falling edge
Input capture at
both edges
Capture input
source is
channel
1/count clock
Input capture at
TCNT1 count-
up/count-down
Note: 1. When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev. 5.00 Sep 11, 2006 page 391 of 916
REJ09B0332-0500