SH7065 Datasheet, PDF (12/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

6.2 Interrupt Sources ............................................................................................................... 180
6.2.1 NMI Interrupt....................................................................................................... 180
6.2.2 User Break Interrupt ............................................................................................ 180
6.2.3 External Interrupts................................................................................................ 180
6.2.4 On-Chip Peripheral Module Interrupts ................................................................ 182
6.2.5 Interrupt Exception Vectors and Priority Order ................................................... 182
6.3 Register Descriptions ........................................................................................................ 188
6.3.1 Interrupt Priority Registers A to L (IPRA to IPRL) ............................................. 188
6.3.2 Interrupt Control Register 1 (ICR1) ..................................................................... 190
6.3.3 Interrupt Control Register 2 (ICR2) ..................................................................... 191
6.3.4 IRQ Status Register (ISR) .................................................................................... 192
6.4 Operation........................................................................................................................... 194
6.4.1 Interrupt Operation Sequence .............................................................................. 194
6.4.2 Interrupt Response Time ...................................................................................... 196
6.4.3 Stack Status after Interrupt Exception Handling .................................................. 198
6.5 Sampling of Signals IRQ3 to IRQ0 in IRL Mode ............................................................. 198
6.6 Data Transfer by Means of Interrupt Request Signal ........................................................ 199
6.6.1 To Designate a Source as a DMAC Activation Source,
Not a CPU Interrupt Source ................................................................................. 200
6.6.2 To Designate a Source as a CPU Interrupt Source,
Not a DMAC Activation Source .......................................................................... 200
6.7 Usage Notes ...................................................................................................................... 201
6.7.1 IRQ3 to IRQ0 Sampling and Interrupt Source Determination
in IRL Interrupt Mode.......................................................................................... 201
6.7.2 IRQ Pin Noise Cancellation Function .................................................................. 201
Section 7 User Break Controller (UBC) ....................................................................... 203
7.1 Overview........................................................................................................................... 203
7.1.1 Features................................................................................................................ 203
7.1.2 Block Diagram ..................................................................................................... 204
7.1.3 Register Configuration ......................................................................................... 205
7.2 Register Descriptions ........................................................................................................ 205
7.2.1 User Break Address Register (UBAR)................................................................. 205
7.2.2 User Break Address Mask Register (UBAMR) ................................................... 207
7.2.3 User Break Bus Cycle Register (UBBR) ............................................................. 208
7.3 Operation........................................................................................................................... 211
7.3.1 User Break Operation Sequence .......................................................................... 211
7.3.2 Instruction Fetch Cycle Break.............................................................................. 212
7.3.3 Data Access Cycle Break ..................................................................................... 212
7.3.4 X Memory Bus or Y Memory Bus Cycle Break .................................................. 213
7.3.5 Program Counter (PC) Value Saved .................................................................... 213
Rev. 5.00 Sep 11, 2006 page xii of xxii