SH7065 Datasheet, PDF (531/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 13 Watchdog Timer
Bit 7—Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00 when in
interval timer mode. This flag is not set in watchdog timer (WDT) mode.
Bit 7: OVF
0
1
Description
No TCNT overflow in interval timer mode
TCNT overflow has occurred in interval timer mode
[Clearing condition]
Cleared by reading OVF, then writing 0 to OVF
(Initial value)
Bit 6—Timer Mode Select (WT/IT): Selects whether the WDT is used as a watchdog timer or
interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request
(ITI) when TCNT overflows. If used as a watchdog timer, the WDT generates the WDTOVF
signal when TCNT overflows.
Bit 6: WT/IT
Description
0
Interval timer mode: Interval timer interrupt (ITI) request is sent to CPU when
TCNT overflows
(Initial value)
1
Watchdog timer mode: WDTOVF signal is output externally when TCNT
overflows
Note: For details of what happens when TCNT overflows during watchdog timer operation, see
section 13.2.3, Reset Control/Status Register (RSTCSR).
Bit 5—Timer Enable (TME): Selects whether the timer runs or is halted.
Bit 5: TME
0
1
Description
Timer disable: TCNT is initialized to H'00 and halted
Timer enable: TCNT counts up
(Initial value)
Bits 4 and 3—Reserved: These bits are always read as 1 and should only be written with 1.
Rev. 5.00 Sep 11, 2006 page 509 of 916
REJ09B0332-0500