SH7065 Datasheet, PDF (738/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 18 I/O Ports (I/O)
18.6.3 Port E Data Register L (PEDRL)
Bit: 15
14
13
12
11
10
9
8
PE15DR PE14DR PE13DR PE12DR —
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Port E data register L (PEDRL) is a 16-bit readable/writable register that stores port E data. Bits
PE15DR to PE12DR correspond to pins PE15/IRQ7 to PE12/IRQ4.
When a pin functions as a general output, if a value is written to PEDRL, that value is output
directly from the pin, and if PEDRL is read, the register value is returned directly regardless of the
pin state.
When a pin functions as a general input, if PEDRL is read the pin state, not the register value, is
returned directly. If a value is written to PEDRL, although that value is written into PEDRL it
does not affect the pin state. Table 18.10 summarizes port E data register read/write operations.
PEDRL is initialized by an external power-on reset, but is not initialized by a WDT reset or in
standby mode or sleep mode.
Table 18.10 Port E Data Register (PEDR) Read/Write Operations
PEIOR
0
1
Pin Function
General input
Read
Pin state
Other than general
input
General output
Other than general
output
Undefined
PEDR value
PEDR value
Write
Value is written to PEDR, but does not
affect pin state
Value is written to PEDR, but does not
affect pin state
Write value is output from pin
Value is written to PEDR, but does not
affect pin state
Rev. 5.00 Sep 11, 2006 page 716 of 916
REJ09B0332-0500